1. Technical Field
The present invention relates to a logic circuits in general, and in particular to transconductor circuits. Still more particularly, the present invention relates to a programmable linear transconductor circuit.
2. Description of the Prior Art
A hard drive typically includes a preamplifier, a read channel, a write channel, a servo controller, a motor control circuit, a read-only memory (ROM), a random-access memory (RAM), and a variety of disk control circuitry for controlling various operations of the hard drive. Generally speaking, the read channel of a hard drive requires a low-pass filter circuit for reducing wideband noise and for shaping readback signals. Such low-pass filter, which is also a continuous-time filter (CTF) located at the front-end of a read channel, is commonly built from a number of tunable transconductance stages. Each transconductance stage includes an operational transconductance amplifier (OTA).
The cutoff frequency of a gm*C filter is proportional to the product of the transconductance, gm, and the load capacitance, C, of all the OTA transconductors within the gm*C filter. For read channel applications, the cutoff frequency of a gm*C filter must be programmable over at least a 3-to-1 range in two separate modes of operation, namely, a servo mode and a read mode. The two modes of operation require the cutoff frequency range of a gm*C filter to be at least a 5-to-1 ratio. For example, a read channel has an overall cutoff frequency range of 30 MHz to 200 MHz. In order to achieve the above-mentioned cutoff frequency range, a 6-bit current digital-to-analog converter (DAC) is programmed to adjust to tail currents in the OTA transconductors over a range of about 10-to-1. The present disclosure describes a programmable linear transconductor circuit to be utilized in a gm*C filter within a read channel of a hard drive.
In accordance with a preferred embodiment of the present invention, a linear transconductor circuit includes a first current source and a second current source, a first group of transistors and a second group of transistors, a first load coupled to the first group of transistors, and a second load coupled to the second group of transistors, and a first group of switches and a second group of switches. Each switch in the first group of switches is selectively connected to a transistor from the first group of transistors to the first current source or the second current source. Similarly, each switch in the second group of switches is selectively connected to a transistor from the second group of transistors to the first current source or the second current source, accordingly.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.